LaSiOₓ- and Al₂O₃-Inserted Low-Temperature Gate-Stacks for Improved BTI Reliability in 3-D Sequential Integration

Sequential 3-D stacking of multiple CMOS device tiers in a single fabrication flow requires the development reliable high- ${k}$ /metal gate (HKMG) stacks at reduced thermal budget (<525 °C). The omission customary high-temperature gate-stack annealing results excessive dielectric defect densities. We have recently demonstrated on MOS capacitors insertion “defect decoupling” layers–LaSiOx for nMOS and Al2O3 pMOS–at interface between SiO2 HfO2 as promising approach to engineer band lineup minimize charge trapping improved bias-temperature-instability (BTI) reliability. In this article, we demonstrate planar transistors, which allows assessing impact decoupling carrier mobility. First, comparative study LaSiOx is performed, highlighting different strategies improving positive BTI (PBTI) negative (NBTI) Second, comprehensive investigation effects conducted with focus reliability channel mobility: lack penalty (Al2O3) or even mobility (LaSiOx) reported dipole-inserted stacks. Furthermore, explore simplified dual integration flow. A severe PBTI observed if an layer (for hole trap decoupling) deposited gate-stack, top beneficial electron decoupling). contrast, pMOS found be more tolerant presence residual layer, suggesting viable strategy integration. Finally, improvement validated also FinFET test vehicle.